#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/msm/msm-bus-ids.h>
#include <dt-bindings/clock/qcom,videocc-kona.h>

&soc {
	msm_vidc: qcom,vidc@aa00000 {
		compatible = "qcom,msm-vidc", "qcom,kona-vidc";
		status = "ok";
		sku-index = <0>;
		reg = <0x0aa00000 0x00100000>;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

		/* IOMMU Config */
		#address-cells = <1>;
		#size-cells = <1>;

		/* LLCC Cache */
		cache-slice-names = "vidsc0";

		/* Supply */
		iris-ctl-supply = <&mvs0c_gdsc>;
		vcodec-supply = <&mvs0_gdsc>;

		/* Clocks */
		clock-names = "gcc_video_axi0",
			"core_clk", "vcodec_clk";
		clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
			<&clock_videocc VIDEO_CC_MVS0C_CLK>,
			<&clock_videocc VIDEO_CC_MVS0_CLK>;
		qcom,proxy-clock-names = "gcc_video_axi0",
					"core_clk", "vcodec_clk";
		/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
		qcom,clock-configs = <0x0 0x1 0x1>;
		qcom,allowed-clock-rates = <239999999 338000000
						366000000 444000000>;
		resets = <&clock_gcc GCC_VIDEO_AXI0_CLK_ARES>,
			<&clock_videocc VIDEO_CC_MVS0C_CLK_ARES>;
		reset-names = "video_axi_reset", "video_core_reset";

		qcom,reg-presets = <0xB0088 0x0>;

		/* Buses */
		bus_cnoc {
			compatible = "qcom,msm-vidc,bus";
			label = "cnoc";
			qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
			qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
			qcom,mode = "performance";
			qcom,bus-range-kbps = <762 762>;
		};

		venus_bus_ddr {
			compatible = "qcom,msm-vidc,bus";
			label = "venus-ddr";
			qcom,bus-master = <MSM_BUS_MASTER_LLCC>;
			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
			qcom,mode = "venus-ddr";
			qcom,bus-range-kbps = <762 15000000>;
		};

		venus_bus_llcc {
			compatible = "qcom,msm-vidc,bus";
			label = "venus-llcc";
			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
			qcom,bus-slave = <MSM_BUS_SLAVE_LLCC>;
			qcom,mode = "venuc-llcc";
			qcom,bus-range-kbps = <2288 15000000>;
		};

		/* MMUs */
		non_secure_cb {
			compatible = "qcom,msm-vidc,context-bank";
			label = "venus_ns";
			iommus = <&apps_smmu 0x2100 0x0400>;
			qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
			qcom,iommu-faults = "non-fatal";
			qcom,iommu-pagetable = "LLC";
			buffer-types = <0xfff>;
			virtual-addr-pool = <0x25800000 0xba800000>;
		};

		secure_non_pixel_cb {
			compatible = "qcom,msm-vidc,context-bank";
			label = "venus_sec_non_pixel";
			iommus = <&apps_smmu 0x2104 0x0400>;
			qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
			qcom,iommu-faults = "non-fatal";
			qcom,iommu-pagetable = "LLC";
			qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
			buffer-types = <0x480>;
			virtual-addr-pool = <0x01000000 0x24800000>;
			qcom,secure-context-bank;
		};

		secure_bitstream_cb {
			compatible = "qcom,msm-vidc,context-bank";
			label = "venus_sec_bitstream";
			iommus = <&apps_smmu 0x2101 0x0404>;
			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
			qcom,iommu-faults = "non-fatal";
			qcom,iommu-pagetable = "LLC";
			qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
			buffer-types = <0x241>;
			virtual-addr-pool = <0x00500000 0xdfb00000>;
			qcom,secure-context-bank;
		};

		secure_pixel_cb {
			compatible = "qcom,msm-vidc,context-bank";
			label = "venus_sec_pixel";
			iommus = <&apps_smmu 0x2103 0x0400>;
			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
			qcom,iommu-faults = "non-fatal";
			qcom,iommu-pagetable = "LLC";
			qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
			buffer-types = <0x106>;
			virtual-addr-pool = <0x00500000 0xdfb00000>;
			qcom,secure-context-bank;
		};
	};
};
